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1 document # sram119 rev g revised june 2007 p4c1256 high speed 32k x 8 static cmos ram high speed (equal access and cycle times) ? 12/15/20/25/35 ns (commercial) ? 15/20/25/35/45 ns (industrial) ? 20/25/35/45/55/70 ns (military) low power single 5v10% power supply easy memory expansion using ce ce ce ce ce and oe oe oe oe oe inputs common data i/o three-state outputs functional block diagram pin configurations 1519b fully ttl compatible inputs and outputs advanced cmos technology fast t oe automatic power down packages ?28-pin 300 mil dip, soj, tsop ?28-pin 300 mil ceramic dip ?28-pin 600 mil ceramic dip ?28-pin cerpack ?28-pin sop ?28-pin lcc (350 mil x 550 mil) ?32-pin lcc (450 mil x 550 mil) features description the p4c1256 is a 262,144-bit high-speed cmos static ram organized as 32kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times as fast as 12 nanoseconds permit greatly enhanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1256 is a member of a family of pace ram? prod- ucts offering fast access times. dip (p5, c5, c5-1, d5-2), soj (j5), sop (s11-1, s11-3) cerpack (f4) similar see end of datasheet for lcc and tsop pin configurations. the p4c1256 device provides asynchronous operation with matching access and cycle times. memory loca- tions are specified on address pins a 0 to a 14 . reading is accomplished by device selection ( ce and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. package options for the p4c1256 include 28-pin 300 mil dip, soj and tsop packages. for military tempera- ture range, ceramic dip and lcc packages are avail- able.
p4c1256 page 2 of 17 document # sram119 rev g p4c1256 maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce v ih mil. v cc = max, ind./com?l. f = max., outputs open ___ ___ 45 30 20 10 ___ ___ ce v hc mil. v cc = max, ind./com?l. f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 industrial grade(2) ambient temperature gnd v cc 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% ?55c to +125c military symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 8 10 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input leakage current test conditions v cc = max. mil. v in = gnd to v cc ind./com?l. v cc = max., mil. ce = v ih , ind./com?l. v out = gnd to v cc min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 +10 +5 +10 +5 typ. commercial ?40c to +85c 0c to +70c unit v v v v a a ma ma v ol output low voltage (ttl load) i ol = +8 ma, v cc = min. 0.4 v output high voltage (ttl load) v oh i oh = ?4 ma, v cc = min. 2.4 v output leakage current p4c1256l ___ ___ 30 n/a 10 n/a ___ ___ min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) ?5 n/a ?5 n/a max v cc +0.5 0.8 v cc +0.5 0.2 +5 n/a +5 n/a 0.4 2.4 n/a = not applicable
p4c1256 page 3 of 17 document # sram119 rev g *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . i cc symbol parameter temperature range dynamic operating current* commercial industrial military n/a n/a ?15 n/a ?12 ?20 ?25 ?35 ?45 ?55 ?70 unit n/a ma ma ma power dissipation characteristics vs. speed n/a n/a n/a n/a 170 160 170 155 165 170 150 145 160 155 150 150 150 155 160 165 data retention characteristics (p4c1256l military temperature only) symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditons ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 2.0 0 t rc typ.* v cc = 2.0v 3.0v max v cc = 2.0v 3.0v unit 10 15 100 200 v a ns ns *t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. data retention waveform
p4c1256 page 4 of 17 document # sram119 rev g ac electrical characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) sym. t rc t aa t ac t oh t lz t hz t oe t olz t ohz t pu t pd parameter read cycle time address access time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z output enable low to low z output enable high to high z chip enable to power up time chip disable to power down time output enable low to data valid min max min max min max min max min max min max min max min max -20 -25 -35 -45 -55 -70 -12 -15 unit 12 2 0 0 12 12 2 5 5 5 12 15 2 2 0 0 15 15 8 7 7 15 20 2 2 0 0 20 20 9 9 9 20 25 3 3 0 0 25 25 11 10 11 20 35 3 3 0 0 35 35 15 15 15 20 45 3 3 0 0 45 45 20 20 20 25 55 3 3 0 0 55 55 25 25 25 30 70 3 3 0 0 70 70 30 30 30 35 ns ns ns ns ns ns ns ns ns ns ns
p4c1256 page 5 of 17 document # sram119 rev g timing waveform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 ( ce ce ce ce ce controlled) (5,7) notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 1 ( oe oe oe oe oe controlled) (5)
p4c1256 page 6 of 17 document # sram119 rev g -35 ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) sym. t wc t cw t as t wp t ah t dw t dh parameter write cycle time chip enable time to end of write address set-up time write pulse width address hold time date hold time data valid to end of write min max min max min max min max min max min max min max min max -20 -25 -45 -55 -70 -12 -15 unit 12 0 0 9 0 8 15 11 0 20 15 0 25 0 18 0 35 0 22 0 45 0 25 0 55 0 30 0 70 0 35 0 9 10 0 9 15 0 11 18 20 0 13 22 25 0 15 30 35 0 20 35 40 0 25 40 45 0 30 ns ns ns ns ns ns ns ns t aw address valid to end of write 9 10 15 00 write enable to output in high z t wz 7 8 10 11 15 18 25 30 ns output active from end of write t ow 33335500ns timing waveform of write cycle no. 1 ( we we we we we controlled) (10,11)
p4c1256 page 7 of 17 document # sram119 rev g notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the first transitioning address. timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (10)
p4c1256 page 8 of 17 document # sram119 rev g input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 ac test conditions figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: because of the ultra-high speed of the p4c1256, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). write active read truth table mode standby standby d out disabled standby power i/o we we we we we oe oe oe oe oe ce ce ce ce ce high z high z d out high z x x h h l x x h l x h l l l standby active active high z x
p4c1256 page 9 of 17 document # sram119 rev g ordering information selection guide the p4c1256 is available in the following temperature, speed and package options. the p4c1256l is available only over the military temperature range. ** * military temperature range with mil-std-883, class b processing. ** for rohs compliant plastic products, the suffix "lf" (lead free) should be added to the part number. n/a = not available 12 15 20 25 35 45 55 70 plastic dip -12pc -15pc -20pc -25pc -35pc n/a n/a n/a plastic soj -12jc -15jc -20jc -25jc -35jc n/a n/a n/a plastic tsop -12tc -15tc -20tc -25tc -35tc n/a n/a n/a plastic sop (s11-1) -12sc -15sc -20sc -25sc -35sc n/a n/a n/a plastic sop (s11-3) -12ssc -15ssc -20ssc -25ssc -35ssc n/a n/a n/a plastic dip n/a -15pi -20pi -25pi -35pi -45pi n/a n/a plastic soj n/a -15ji -20ji -25ji -35ji -45ji n/a n/a plastic tsop n/a -15ti -20ti -25ti -35ti -45ti n/a n/a plastic sop (s11-1) n/a -15si -20si -25si -35si -45si n/a n/a plastic sop (s11-3) n/a -15ssi -20ssi -25ssi -35ssi -45ssi n/a n/a speed temperature ra nge package commercial industrial
p4c1256 page 10 of 17 document # sram119 rev g lcc pin configurations 28 lcc (l5) 32 lcc (l6) tsop (t1) selection guide (continued) 12 15 20 25 35 45 55 70 side brazed dip (300 mil) n/a n/a -20cm -25cm -35cm -45cm -55cm -70cm side brazed dip (600 mil) n/a n/a -20cwm -25cwm -35cwm -45cwm -55cwm -70cwm ceramic dip n/a n/a -20dm -25dm -35dm -45dm -55dm -70dm cerpack n/a n/a -20fm -25fm -35fm -45fm -55fm -70fm lcc (28-pin) n/a n/a -20l28m -25l28m -35l28m -45l28m -55l28m -70l28m lcc (32-pin) n/a n/a -20l32m -25l32m -35l32m -45l32m -55l32m -70l32m side brazed dip (300 mil) n/a n/a -20cmb -25cmb -35cmb -45cmb -55cmb -70cmb side brazed dip (600 mil) n/a n/a -20cwmb -25cwmb -35cwmb -45cwmb -55cwmb -70cwmb ceramic dip n/a n/a -20dmb -25dmb -35dmb -45dmb -55dmb -70dmb cerpack n/a n/a -20fmb -25fmb -35fmb -45fmb -55fmb -70fmb lcc (28-pin) n/a n/a -20l28mb -25l28mb -35l28mb -45l28mb -55l28mb -70l28mb lcc (32-pin) n/a n/a -20l32mb -25l32mb -35l32mb -45l32mb -55l32mb -70l32mb speed military temperature military processed* temperature range package
p4c1256 page 11 of 17 document # sram119 rev g pkg # # pins symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c5 28 (300 mil) 0.300 bsc 0.100 bsc side brazed ceramic dual in-line package (300 mils) side brazed ceramic dual in-line package (600 mils) pkg # # pins symbol min max a - 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.490 e 0.500 0.610 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - c5-1 28 (600 mil) 0.600 bsc 0.100 bsc
p4c1256 page 12 of 17 document # sram119 rev g pkg # # pins symbol min max a 0.060 0.090 b 0.015 0.022 c 0.004 0.009 d-0.730 e 0.330 0.380 e k 0.005 0.018 l 0.250 0.370 q 0.026 0.045 s-0.085 s1 0.005 - f4 28 0.050 bsc cerpack ceramic flat package pkg # # pins symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 d5-2 28 (300 mil) 0.300 bsc 0.100 bsc cerdip dual in-line package
p4c1256 page 13 of 17 document # sram119 rev g pkg # # pins symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e e e1 0.292 0.300 e2 q0.025- j5 28 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc soj small outline ic package pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref l5 28 0.200 bsc 0.100 bsc rectangular leadless chip carrier (28 pins)
p4c1256 page 14 of 17 document # sram119 rev g pkg # # pins symbol min max a-0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p5 28 (300 mil) plastic dual in-line package pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 d2 d3 - 0.458 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne l6 32 0.300 bsc 0.150 bsc 0.020 ref 7 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref rectangular leadless chip carrier (32 pins)
p4c1256 page 15 of 17 document # sram119 rev g tsop thin small outline package (8 x 13.4 mm) pkg # # pins symbol min max a 0.039 0.047 a 2 0.036 0.040 b 0.007 0.011 d 0.461 0.469 e 0.311 0.319 e h d 0.520 0.535 t1 28 0.022 bsc pkg # # pins symbol min max a 0.093 0.104 a1 0.004 0.012 b2 0.013 0.020 c 0.009 0.012 d 0.696 0.712 e e 0.291 0.299 h 0.394 0.419 h 0.010 0.029 l 0.016 0.050 0 8 s11-1 28 (300 mil) 0.050 bsc soic/sop small outline ic package
p4c1256 page 16 of 17 document # sram119 rev g soic/sop small outline ic package pkg # # pins symbol min max a 0.094 0.110 a1 0.002 0.014 b 0.014 0.020 c 0.008 0.012 d 0.702 0.710 e e 0.291 0.300 h 0.463 0.477 h 0.010 0.029 l 0.020 0.042 0 8 s11-3 28 (300 mil) 0.050 bsc
p4c1256 page 17 of 17 document # sram119 rev g revisions document number : sram119 document title : high speed 32k x 8 static cmos ram rev. issue date orig. of change description of change or 1997 rkk new data sheet a oct-05 jdb change logo to pyramid b oct-05 jdb added sop package c apr-06 jdb added lead-free ordering information. d may-06 jdb added pdip to ordering information diagram e jun-06 jdb added ceramic dip package f aug-06 jdb updated soj package information g jun-07 jdb corrected sop package information

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